Name
Abstract | ||
|---|---|---|
Based on a concept of equivalent capacitance, previously developed, we present a novel analytical linear representation of internal power dissipation components in CMOS structures. An extension to gates is proposed using an equivalent inverter representation, deduced from the evaluation of an equivalent transistor for serial transistors arrays. Validation of this model is given by comparing the calculated results to the simulated values (using foundries model card), with different design conditions, implemented in 0.25µm and 0.18µm CMOS processes. Application is given to delay and power optimisation of buffer and path. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1007/3-540-45373-3_13 | PATMOS |
Keywords | Field | DocType |
calculated result,equivalent capacitance,internal power dissipation component,foundries model card,equivalent transistor,cmos structure,internal power dissipation modeling,equivalent inverter representation,novel analytical linear representation,power optimisation,m cmos,submicronic cmos design,power dissipation | Inverter,Capacitance,Computer science,Dissipation,Computer Aided Design,Circuit design,Electronic engineering,CMOS,Minification,Transistor | Conference |
Volume | ISSN | ISBN |
1918 | 0302-9743 | 3-540-41068-6 |
Citations | PageRank | References |
2 | 0.48 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Philippe Maurine | 1 | 276 | 40.44 |
| M. Rezzoug | 2 | 2 | 0.82 |
| Daniel Auvergne | 3 | 145 | 31.67 |