Name
Abstract | ||
|---|---|---|
A dynamically reconfigurable on-chip multiprocessor architecture is presented, which can be adapted to changing application demands and to faults detected at run-time. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC with minimal area and performance overhead. Adaptability of the architecture relies on a self-optimizing reconfiguration of the MPSoC at run-time. The resource-efficiency of the proposed architecture is analyzed based on FPGA and ASIC prototypes. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/AHS.2009.52 | AHS |
Keywords | Field | DocType |
fault tolerance,scalable architecture,asic prototype,mpsocs targeting resource efficiency,self-optimizing reconfiguration,hierarchical network-on-chip,minimal area,lightweight embedded risc processor,performance overhead,dynamically reconfigurable on-chip multiprocessor,application demand,proposed architecture,fpga,field programmable gate arrays,chip,registers,fault tolerant,network on chip,reduced instruction set computing,fault detection,switches,system on a chip | Computer architecture,Reconfigurability,System on a chip,Computer science,Parallel computing,Network on a chip,Application-specific integrated circuit,Real-time computing,Reduced instruction set computing,Fault tolerance,MPSoC,Control reconfiguration | Conference |
Citations | PageRank | References |
5 | 0.48 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mario Porrmann | 1 | 420 | 50.91 |
| Madhura Purnaprajna | 2 | 47 | 6.34 |
| Christoph Puttmann | 3 | 36 | 3.90 |