Paper Info
Title
Post-route gate sizing for crosstalk noise reduction
Abstract
Gate sizing is a practical and a feasible crosstalk noise repair technique in the post route design stage, especially for block level sea-of-gates designs. The difficulty in gate sizing for noise reduction is that by increasing a driver size, noise at the driver output is reduced, but noise injected by that driver on other nets is increased. This can create cyclical dependencies between nets in the circuit with noise violations. In this paper, we propose a fast and effective heuristic post-route gate sizing algorithm that uses a graph representation of the noise dependencies between nodes. Our method utilizes gate sizing in both directions and works in linear time as a function of the number of gates. The effectiveness of the algorithm is shown on several industrial high performance designs.
Year
DOI
Venue
2003
10.1145/775832.776071
international symposium on quality electronic design
Keywords
DocType
ISSN
driver size,method utilizes gate,difficulty ingate,crosstalk noise reduction,feasible crosstalk noisecorrection technique,driver output,especiallyfor block level sea-of-gates,noise injectedby,post-route gate,noise dependency,post-route gate sizing,feasible crosstalk noise repair,effectiveheuristic post-route gate,block level sea-of-gates design,gate sizing,crosstalk noise repair,effective heuristic post-route gate,ourmethod utilizes gate,noise violation,noise reduction,heuristic algorithm,network routing,graph representation,integrated circuit design,graph theory,linear time,mathematical model,crosstalk,routing,capacitance
Conference
0738-100X
ISBN
Citations 
PageRank 
1-58113-688-9
14
0.88
References 
Authors
20
7
Name
Order
Citations
PageRank
Becer, M.R.116914.33
David Blaauw28916823.47
Ilan Algor3281.68
R. Panda41002111.69
Chanhee Oh535343.20
Vladimir Zolotov61367109.07
Ibrahim N. Hajj757279.52