Name
Abstract | ||
|---|---|---|
Post-silicon validation is used to identify design errors in silicon. Its main limitation is real-time observability of the circuit's internal nodes. In this paper we introduce a novel design-for-debug architecture which automatically allocates distributed trace buffers to handle debug data acquisition requests from multiple sources located in different cores. Using resource-efficient and intelligent control placed on-chip, we show how real-time observability can be improved, thus helping bridge the gap between pre-silicon verification and post-silicon validation for SOC designs. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TEST.2008.4700594 | 2008 IEEE INTERNATIONAL TEST CONFERENCE, VOLS 1 AND 2, PROCEEDINGS |
Keywords | Field | DocType |
intelligent control,system on a chip,integrated circuit design,real time systems,system on chip,resource management,chip,data acquisition,logic design,real time,observability,post silicon validation | Logic synthesis,Intelligent control,Observability,System on a chip,Post-silicon validation,Computer science,Data acquisition,Electronic engineering,Real-time computing,Integrated circuit design,Debugging,Embedded system | Conference |
ISSN | Citations | PageRank |
1089-3539 | 28 | 1.20 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ho Fai Ko | 1 | 234 | 14.44 |
| Adam B. Kinsman | 2 | 141 | 10.05 |
| Nicola Nicolici | 3 | 807 | 59.91 |