Name
Abstract | ||
|---|---|---|
This article describes a new method for constructing and analyzing architectures that can track all information flows within a processor, including explicit, implicit, and timing flows. The key to this approach is a novel gate-level information-flow-tracking method that provides a way to create complex logical structures with well-defined information-flow properties. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/MM.2010.17 | IEEE Micro |
Keywords | Field | DocType |
well-defined information-flow property,information flow,complex logical structure,new method,gate-level information-flow tracking,novel gate-level,secure architectures,timing flow,information management,security architecture,covert channels,covert channel,logic gates,tracking,logic design | Logic synthesis,Information flow (information theory),Information management,Logic gate,Computer science,Parallel computing,Covert channel,Real-time computing | Journal |
Volume | Issue | ISSN |
30 | 1 | 0272-1732 |
Citations | PageRank | References |
6 | 0.55 | 6 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohit Tiwari | 1 | 445 | 23.94 |
| Xun Li | 2 | 127 | 5.94 |
| Hassan M. G. Wassel | 3 | 190 | 8.99 |
| Bita Mazloom | 4 | 8 | 0.92 |
| Shashidhar Mysore | 5 | 45 | 5.23 |
| Frederic T. Chong | 6 | 1428 | 130.07 |
| Timothy Sherwood | 7 | 1921 | 123.28 |