| PyLSE: A Pulse-Transfer Level Language for Superconductor Electronics | 0 | 0.34 | 2022 |
| Technical perspective: A recipe for protecting against speculation attacks | 0 | 0.34 | 2021 |
| In-sensor classification with boosted race trees | 0 | 0.34 | 2021 |
| Trace Wringing for Program Trace Privacy | 0 | 0.34 | 2020 |
| Agile Hardware Development and Instrumentation With PyRTL | 2 | 0.37 | 2020 |
| Efficient Uncertainty Modeling for System Design via Mixed Integer Programming | 0 | 0.34 | 2019 |
| PyRTL in Early Undergraduate Research | 0 | 0.34 | 2019 |
| Neural Network Model Extraction Attacks in Edge Devices by Hearing Architectural Hints. | 1 | 0.35 | 2019 |
| An Architecture for Analysis. | 0 | 0.34 | 2018 |
| Quantitative Analysis of Timing Channel Security in Cryptographic Hardware Design. | 3 | 0.37 | 2018 |
| Architectural Risk. | 0 | 0.34 | 2018 |
| Information Leakage in Arbiter Protocols. | 0 | 0.34 | 2018 |
| High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing. | 0 | 0.34 | 2018 |
| A 4-mm2 180-nm-CMOS 15-Giga-cell-updates-per-second DNA sequence alignment engine based on asynchronous race conditions. | 0 | 0.34 | 2017 |
| Thermal-aware, heterogeneous materials for improved energy and reliability in 3D PCM architectures. | 0 | 0.34 | 2017 |
| Hardware-Assisted Context Management for Accelerator Virtualization: A Case Study with RSA. | 0 | 0.34 | 2016 |
| Energy efficient computation with asynchronous races. | 1 | 0.35 | 2016 |
| Report on the NSF Workshop on Formal Methods for Security. | 3 | 0.38 | 2016 |
| Quantifying Timing-Based Information Flow in Cryptographic Hardware | 4 | 0.45 | 2015 |
| Leveraging Gate-Level Properties to Identify Hardware Timing Channels | 14 | 0.78 | 2014 |
| Networks on Chip with Provable Security Properties | 13 | 0.93 | 2014 |
| Sapper: a language for hardware-level security policy enforcement | 33 | 0.99 | 2014 |
| Gate-Level Information Flow Tracking for Security Lattices | 5 | 0.45 | 2014 |
| Race Logic: A hardware acceleration for dynamic programming algorithms | 19 | 0.85 | 2014 |
| Memristors for neural branch prediction: a case study in strict latency and write endurance challenges | 10 | 0.54 | 2013 |
| A practical testing framework for isolating hardware timing channels | 2 | 0.36 | 2013 |
| Position paper: Sapper -- a language for provable hardware policy enforcement | 1 | 0.36 | 2013 |
| SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip | 42 | 1.37 | 2013 |
| Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip | 3 | 0.41 | 2013 |
| Opportunities and Challenges of Using Plasmonic Components in Nanophotonic Architectures | 5 | 0.52 | 2012 |
| Analysis of performance versus security in hardware realizations of small elliptic curves for lightweight applications. | 3 | 0.38 | 2012 |
| A qualitative security analysis of a new class of 3-d integrated crypto co-processors | 10 | 0.65 | 2012 |
| On the Complexity of Generating Gate Level Information Flow Tracking Logic | 9 | 0.53 | 2012 |
| Mobile vision-based sketch recognition with SPARK | 0 | 0.34 | 2012 |
| Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security | 51 | 1.71 | 2011 |
| Caisson: a hardware description language for secure information flow | 38 | 1.09 | 2011 |
| Information flow isolation in I2C and USB | 15 | 0.72 | 2011 |
| Hybrid CMOS/nanodevice circuits for high throughput pattern matching applications | 14 | 0.87 | 2011 |
| Preventing PCM banks from seizing too much power | 49 | 1.53 | 2011 |
| Exploiting Data Similarity to Reduce Memory Footprints | 11 | 0.56 | 2011 |
| Fighting fire with fire: modeling the datacenter-scale effects of targeted superlattice thermal management | 12 | 0.68 | 2011 |
| Data analysis on interactive whiteboards through sketch-based interaction | 26 | 0.95 | 2011 |
| Function flattening for lease-based, information-leak-free systems | 0 | 0.34 | 2010 |
| Theoretical analysis of gate level information flow tracking | 12 | 0.74 | 2010 |
| Secure information flow analysis for hardware design: using the right abstraction for the job | 4 | 0.42 | 2010 |
| Hardware assistance for trustworthy systems through 3-D integration | 8 | 0.58 | 2010 |
| Hardware trust implications of 3-D integration | 4 | 0.50 | 2010 |
| Security Primitives for Reconfigurable Hardware-Based Systems | 6 | 0.50 | 2010 |
| VrtProf: Vertical Profiling for System Virtualization | 3 | 0.48 | 2010 |
| Gate-Level Information-Flow Tracking for Secure Architectures | 6 | 0.55 | 2010 |
