Paper Info
Title
A 40-Nm Resilient Cache Memory For Dynamic Variation Tolerance Delivering X91 Failure Rate Improvement Under 35% Supply Voltage Fluctuation
Abstract
This paper presents a resilient cache memory for dynamic variation tolerance in a 40-nm CMOS. The cache can perform sustained operations under a large-amplitude voltage droop. To realize sustained operation, the resilient cache exploits 7T/14T bit-enhancing SRAM and on-chip voltage/temperature monitoring circuit. 7T/14T bit-enhancing SRAM can reconfigure itself dynamically to a reliable bit-enhancing mode. The on-chip voltage/temperature monitoring circuit can sense a precise supply voltage level of a power rail of the cache. The proposed cache can dynamically change its operation mode using the voltage/temperature monitoring result and can operate reliably under a large-amplitude voltage droop. Experimental result shows that it does not fail with 25% and 30% droop of V-dd and it provides 91 times better failure rate with a 35% droop of V-dd compared with the conventional design.
Year
DOI
Venue
2014
10.1587/transele.E97.C.332
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
design for robustness, cache, variation tolerance, 7T/14T SRAM
Cache,CPU cache,Failure rate,Voltage fluctuation,Electronic engineering,Engineering
Journal
Volume
Issue
ISSN
E97C
4
1745-1353
Citations 
PageRank 
References 
0
0.34
6
Authors
14
Name
Order
Citations
PageRank
Yohei Nakata1295.55
Yuta Kimi211.70
Shunsuke Okumura36312.54
Jinwook Jung4977.01
Takuya Sawada531.56
Taku Toshikawa620.79
Makoto Nagata728576.47
Hirofumi Nakano8113.31
Makoto Yabuuchi94912.38
Hidehiro Fujiwara107212.67
Koji Nii1122344.78
Hiroyuki Kawai12192.21
Hiroshi Kawaguchi133721.08
masahiko yoshimoto1411734.06