Paper Info
Title
Global interconnect trade-off for technology over memory modules to application level: case study
Abstract
In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.
Year
DOI
Venue
2003
10.1145/639929.639954
SLIP
Keywords
Field
DocType
future technology node,delay problem,power hungry wire,application real-time constraint,future technology,memory module level,delay slack,power consumption,case study,application level,technology parameter,real time
Interconnect bottleneck,Computer science,Exploit,Electronic engineering,Real-time computing,Interconnection,Memory organisation,Power consumption,Embedded system,Memory module
Conference
ISBN
Citations 
PageRank 
1-58113-627-7
9
0.75
References 
Authors
10
8
Name
Order
Citations
PageRank
A. Papanikolaou1342.95
M. Miranda214411.00
F. Catthoor389783.95
H. Corporaal416112.77
H. De Man549083.62
David De Roest691.77
M. Stucchi711914.31
Karen Maex814117.63