Name
Abstract | ||
|---|---|---|
Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ... |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VTS.2006.91 | VTS |
Keywords | Field | DocType |
large block,profile fault simulation performance,path delay fault simulation,multiple fault activation cycles,functional test vector suite,multi-cycle delay path,industrial design,scan tests,delay faults,digital circuits | Stuck-at fault,Digital electronics,Computer science,Electronic engineering,Real-time computing,Electronic circuit | Conference |
ISSN | ISBN | Citations |
1093-0167 | 0-7695-2514-8 | 16 |
PageRank | References | Authors |
0.90 | 14 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhuo Zhang | 1 | 70 | 3.49 |
| Sudhakar M. Reddy | 2 | 5747 | 699.51 |
| Irith Pomeranz | 3 | 3829 | 336.84 |
| Xijiang Lin | 4 | 687 | 42.03 |
| Janusz Rajski | 5 | 2460 | 201.28 |