Name
Title | ||
|---|---|---|
Exploration of 3D stacked L2 cache design for high performance and efficient thermal control |
Abstract | ||
|---|---|---|
The three-dimensional (3D) integration enables stacking large memory on top of chip-multi-processors (CMPs). Compared to the 2D case, the extra dimension and high bandwidth provide more options for the design of on-chip memory such as L2 caches. In this work, we study the design of 3D stacked set-associative L2 caches through managing the placement of cache ways. The evaluation results show that the placement has an impact on the performance. In addition, we propose a technique of shadow tag to dynamically adjust the working size of the 3D cache in order to save power and reduce the peak temperature. Evaluation results show that the proposed inter-layer core-based-distribution placement of 3D cache ways is the best design option, when both the performance and thermal management are considered. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1145/1594233.1594306 | ISLPED |
Keywords | Field | DocType |
peak temperature,evaluation result,large memory,efficient thermal control,cache way,extra dimension,best design option,high bandwidth,on-chip memory,l2 cache design,high performance,l2 cache,proposed inter-layer core-based-distribution placement,thermal management,three dimensional,3d,performance,chip | Cache pollution,CPU cache,Computer science,Cache,Page cache,Cache algorithms,Real-time computing,Cache coloring,Bus sniffing,Smart Cache | Conference |
Citations | PageRank | References |
10 | 0.57 | 9 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guangyu Sun | 1 | 1920 | 111.55 |
| Xiaoxia Wu | 2 | 535 | 38.61 |
| Yuan Xie | 3 | 6430 | 407.00 |