Name
Abstract | ||
|---|---|---|
A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1002/cta.720 | International Journal of Circuit Theory and Applications |
Keywords | Field | DocType |
low power,mhz energy dissipation,binary comparator,parallel-prefix architecture,internal node,new fast low-power single-clock-cycle,high speed,v cmos technology,ghz maximum,john wiley,cmos,energy efficient | Arithmetic circuits,Comparator,Dissipation,Computer science,Efficient energy use,Electronic engineering,CMOS,Comparator applications,Cycles per instruction,Electrical engineering,Binary number | Journal |
Volume | Issue | ISSN |
40 | 3 | 0098-9886 |
Citations | PageRank | References |
7 | 0.63 | 8 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fabio Frustaci | 1 | 129 | 17.55 |
| Stefania Perri | 2 | 264 | 33.11 |
| Marco Lanuzza | 3 | 203 | 28.64 |
| Pasquale Corsonello | 4 | 278 | 38.06 |