Fabio Frustaci - Citegraph

Author Info

Name	Affiliation	Papers
FABIO FRUSTACI	Univ Calabria, Dept Elect Comp Sci & Syst, I-87036 Arcavacata Di Rende, Italy	37
Collaborators	Citations	PageRank
17	129	17.55
Referers	Referees	References
303	752	363

Search Limit

100752

Publications (37 rows)

Collaborators (17 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Accuracy Improved Low-Energy Multi-Bit Approximate Adders in QCA	1	0.37	2021
Stereo vision architecture for heterogeneous systems-on-chip	1	0.35	2020
Approximate Multipliers With Dynamic Truncation For Energy Reduction Via Graceful Quality Degradation	0	0.34	2020
A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs	0	0.34	2020
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation	1	0.35	2019
Multimodal background subtraction for high-performance embedded systems	0	0.34	2019
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata.	2	0.41	2017
Approximate SRAMs With Dynamic Energy-Quality Management.	7	0.53	2016
An efficient hardware-oriented stereo matching algorithm.	2	0.35	2016
Design Of Efficient Qca Multiplexers	0	0.34	2016
Better-than-voltage scaling energy reduction in approximate SRAMs via bit dropping and bit reuse	0	0.34	2015
Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology	2	0.42	2015
A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS	0	0.34	2015
Power supply noise in accurate delay model for the sub-threshold domain.	0	0.34	2015
Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology	5	0.50	2015
SRAM for Error-Tolerant Applications With Dynamic Energy-Quality Management in 28 nm CMOS	8	0.54	2015
A novel background subtraction method based on color invariants and grayscale levels	0	0.34	2014
Designing Dynamic Carry Skip Adders: Analysis and Comparison	0	0.34	2014
Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain	5	0.50	2014
Analyzing noise robustness of wide fan-in dynamic logic gates under process variations	1	0.35	2014
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS	15	0.77	2014
Energy-efficient single-clock-cycle binary comparator	7	0.63	2012
Analytical Delay Model Considering Variability Effects in Subthreshold Domain.	11	0.72	2012
Comparative analysis of yield optimized pulsed flip-flops.	9	0.75	2012
Tapered-Vth Approach For Energy-Efficient Cmos Buffers	0	0.34	2011
Optimization and evaluation of tapered-VTH approach for energy-efficient CMOS buffers.	0	0.34	2011
Tapered-Vth Approach for Energy-Efficient CMOS Buffers	4	0.62	2011
Tapered-VTH CMOS buffer design for improved energy efficiency in deep nanometer technology	2	0.41	2011
Impact of Process Variations on Flip-Flops Energy and Timing Characteristics	8	0.86	2010
A new low-power high-speed single-clock-cycle binary comparator	4	0.53	2010
Impact of process variations on pulsed flip-flops: yield improving circuit-level techniques and comparative analysis	6	0.50	2010
Designing High-Speed Adders in Power-Constrained Environments	10	0.77	2009
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications	5	0.61	2009
A new optimized high-speed low-power data-driven dynamic (d3l) 32-bit kogge-stone adder	1	0.36	2009
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation	0	0.34	2008
Techniques for leakage energy reduction in deep submicrometer cache memories	12	0.95	2006
Leakage energy reduction techniques in deep submicron cache memories: a comparative study	0	0.34	2006