Paper Info
Title
Modeling and design exploration of FBDRAM as on-chip memory
Abstract
Compared to the traditional DRAM technology, floating body DRAM (FBDRAM) has many advantages, such as high density, fast access speed, long retention time, etc. More important, FBDRAM is compatible with the traditional CMOS technology. It makes FBDRAM more competitive than other emerging memory technologies to be employed as on-chip memory. The characteristic variance of memory cells caused by process variations, however, has become an obstacle to adopt FBDRAM. In this work, we build a circuit level model of FBDRAM caches with the consideration of process variations. In order to mitigate the impact of process variations, we apply different error correction mechanisms and corresponding architecture-level modifications to FBDRAM caches and study the trade-off among reliability, power consumption, and performance. With this model, we explore the L2 cache design using FBDRAM and compare it with traditional SRAM/eDRAM caches in both circuit and architectural levels1.
Year
DOI
Venue
2012
10.1109/DATE.2012.6176712
DATE
Keywords
Field
DocType
process variation,traditional sram,design exploration,traditional dram technology,memory cell,traditional cmos technology,cache storage,memory technology,dram chips,error correction mechanism,cmos technology,fbdram cache,l2 cache design,floating body dram,integrated circuit design,architecture-level modification,circuit level model,error correction,on-chip memory,model error,integrated circuit,error correction code,routing,error probability,programming,chip,retention time
Dram,Tag RAM,CPU cache,Computer science,Parallel computing,Real-time computing,Static random-access memory,Universal memory,Integrated circuit design,eDRAM,Energy consumption
Conference
ISSN
ISBN
Citations 
1530-1591
978-1-4577-2145-8
3
PageRank 
References 
Authors
0.39
5
3
Name
Order
Citations
PageRank
Guangyu Sun11920111.55
Cong Xu2115448.25
Yuan Xie36430407.00