Name
Abstract | ||
|---|---|---|
The paper presents a current-mode CMOS image sensor embedded smooth spatial filter algorithm. The sensor includes a 66 x 66 pixel array with an on-chip 6-bit analog-to-digital converter that can identify the output value of pixels in gray level resolution. The last row of pixel cells (1 x 66) based on the double sampling is used for reducing fixed pattern noise (FPN). Processing circuits are dedicated for the spatial filter algorithm and support reusability to increase the image processing speed and to reduce the design complexity and chip area. The sensor chip has been designed and implemented in TSMC 0.35 mu m 2P4M CMOS mixed-mode process. Each pixel occupies a area of 15.8 mu m x 10.6 mu m with a rill factor of 37.2%. The power consumption is 35.15mW when the sensor operates at 175 frames/second. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692613 | 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS |
Keywords | Field | DocType |
image sensor,noise reduction,image processing,chip,cmos image sensor,image sensors,spatial filtering,integrated circuit design,spatial resolution | Fixed-pattern noise,Image sensor,Computer science,Image processing,Analog-to-digital converter,Electronic engineering,Chip,CMOS,Pixel,Image resolution | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chia-chun Tsai | 1 | 109 | 23.04 |
| Huang-chi Chou | 2 | 0 | 0.34 |
| Trong-yen Lee | 3 | 98 | 20.70 |
| Rong-shue Hsiao | 4 | 21 | 3.34 |