Name
Title | ||
|---|---|---|
A New Efficient Dcvs Circuit Synthesis Technique Used For An Improved Implementation Of A Serial Parallel Multiplier |
Abstract | ||
|---|---|---|
This paper describes an efficient technique for the design of fault-secure VLSI circuits based on differential cascode voltage switch (DCVS) logic. We propose a new synthesis method for constructing DCVS circuits with a near-optimal transistor count based on binary decision diagrams (BDDs). The time and memory resources required are very low, making the technique practical even for PC-based synthesis tools. This method is the basis for a CAD tool that allows automatic synthesis of fault-secure circuits based on the DCVS technology. We finally present an improved design and implementation of a 2's complement serial/parallel multiplier as an application of the proposed technique and algorithm. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1002/cta.4490230604 | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
Field | DocType | Volume |
Transistor count,Computer science,Cascode,Binary multiplier,Binary decision diagram,Multiplier (economics),Electronic engineering,Electronic circuit,Integrated circuit,Very-large-scale integration | Journal | 23 |
Issue | ISSN | Citations |
6 | 0098-9886 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Theodore Karoubalis | 1 | 12 | 2.70 |
| Kostas Adaos | 2 | 0 | 0.34 |
| George Ph. Alexiou | 3 | 3 | 1.41 |
| Nick Kanopoulos | 4 | 34 | 12.44 |