Name
Abstract | ||
|---|---|---|
Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ATS.2011.33 | Asian Test Symposium |
Keywords | Field | DocType |
small clock delay fault,clock delay faults,stuck-at fault,proposed test generation method,gate transition fault,delay fault,transition fault,launch-on-capture test environment,clock delay fault,detecting transition faults,fault model,clock line,digital circuits,automatic test pattern generation,logic gate,logic gates,integrated circuit,vectors | Stuck-at fault,Automatic test pattern generation,Digital electronics,Logic gate,Fault coverage,Computer science,Real-time computing,Electronic engineering,Fault (power engineering),Electronic circuit,Fault indicator | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-4577-1984-4 | 2 |
PageRank | References | Authors |
0.38 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Shin-ya Kobayashi | 3 | 38 | 8.60 |
| Kewal K. Saluja | 4 | 1483 | 141.49 |