Name
Abstract | ||
|---|---|---|
The 4×4 integer transforms are adopted in the MPEG-4 AVC /H.264 standard. In this paper, two novel signal flow graphs of the 4×4 forward and inverse transforms for H.264 are proposed. A new dynamic reconfigurable architecture without using transpose memory for the multiple transforms is proposed on the basis of the new SFGs. Our design is implemented with 0.18um CMOS technology. Under a clock frequency of 200 Mhz, the architecture allows the real-time processing of 4096×2048 at 30fps with the area cost of 5140 gates and the power dissipation of 15.64 mW. © 2008 IEEE. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746394 | APCCAS |
Keywords | DocType | Volume |
vlsi,hardware,cmos integrated circuits,transform coding,logic gates,computer architecture,inverse problems | Conference | null |
Issue | ISSN | ISBN |
null | null | 978-1-4244-2342-2 |
Citations | PageRank | References |
1 | 0.35 | 4 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Cao | 1 | 48 | 3.96 |
| Hui Hou | 2 | 39 | 3.00 |
| Jinmei Lai | 3 | 145 | 20.38 |
| Jiarong Tong | 4 | 68 | 11.74 |
| Hao Min | 5 | 61 | 5.47 |