Name
Abstract | ||
|---|---|---|
In this paper, we propose a methodology for accelerating application segments by partitioning them between reconfigurable hardware blocks of different granularity. Critical parts are speeded-up on the coarse-grain reconfigurable hardware for meeting the timing requirements of application code mapped on the reconfigurable logic. The reconfigurable processing units are embedded in a generic hybrid system architecture which can model a large number of existing heterogeneous reconfigurable platforms. The fine-grain reconfigurable logic is realized by an FPGA unit, while the coarse-grain reconfigurable hardware by our developed high-performance data-path. The methodology mainly consists of three stages; the analysis, the mapping of the application parts onto fine and coarse-grain reconfigurable hardware, and the partitioning engine. A prototype software framework realizes the partitioning flow. In this work, the methodology is validated using five real-life applications. Analytical partitioning experiments show that the speedup relative to the all-FPGA mapping solution ranges from 1.5 to 4.0, while the specified timing constraints are satisfied for all the applications. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/s10617-006-8732-6 | Design Autom. for Emb. Sys. |
Keywords | Field | DocType |
Hybrid reconfigurable systems,Partitioning,Coarse-grain reconfigurable hardware,FPGA,scheduling | Computer architecture,Scheduling (computing),Computer science,Parallel computing,Field-programmable gate array,Real-time computing,PipeRench,Granularity,Hybrid system,Software framework,Reconfigurable computing,Speedup | Journal |
Volume | Issue | ISSN |
10 | 1 | 0929-5585 |
Citations | PageRank | References |
2 | 0.40 | 20 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michalis D. Galanis | 1 | 94 | 15.60 |
| Athanasios Milidonis | 2 | 42 | 5.51 |
| George Theodoridis | 3 | 30 | 4.79 |
| Dimitrios Soudris | 4 | 369 | 58.95 |
| Costas E Goutis | 5 | 186 | 25.76 |