Paper Info
Title
3D chip stacking with C4 technology
Abstract
Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.
Year
DOI
Venue
2008
10.1147/JRD.2008.5388560
IBM Journal of Research and Development
Keywords
Field
DocType
c4 technology,low power,low latency,conventional c4,reflow process,parallel reflow,conventional chip-placement,thin chip,integration technology,controlled-collapse chip connection,temporary chip attachment operation,chip
Flip chip,System on a chip,Computer science,Electronic packaging,Chip,Electronic engineering,Three-dimensional integrated circuit,Interconnection,Integrated circuit,Stacking
Journal
Volume
Issue
ISSN
52
6
0018-8646
Citations 
PageRank 
References 
6
1.19
2
Authors
14
Name
Order
Citations
PageRank
Dang, B.111022.83
S. L. Wright261.19
P. S. Andry310622.38
E. J. Sprogis412824.81
C. K. Tsang510622.38
M. J. Interrante6434.52
B. C. Webb710622.38
R. J. Polastre89718.50
R. R. Horton99918.83
C. S. Patel1018822.62
A. Sharma1161.19
J. Zheng1261.19
K. Sakuma1311325.43
J. U. Knickerbocker1412431.11