Name
Abstract | ||
|---|---|---|
We describe the hardware implementation of a phase detector module which is used in a heavy ion accelerator for real-time digital data processing. As this high-speed real-time signal processing currently exceeds the performance of the available DSP processors, we are trying to move some functionality into dedicated hardware. We implemented the phase detection algorithm using a pipeline mechanism to process one data value in every clock cycle. We used a pipelined division operation and implemented an optimized table-based arctan as the main core to compute the phase information. As the result, we are able to process the two 400 MHz incoming data streams with low latency and minimal resource allocation. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1007/11802839_1 | LECTURE NOTES IN COMPUTER SCIENCE |
Keywords | Field | DocType |
signal processing,phase detector,low latency,data processing,real time,resource allocation | Lookup table,Digital signal processing,Digital signal processor,Computer science,Digital signal,Field-programmable gate array,Real-time computing,Phase detector,Latency (engineering),Cycles per instruction,Embedded system | Conference |
Volume | ISSN | Citations |
3985 | 0302-9743 | 4 |
PageRank | References | Authors |
0.78 | 4 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andre Guntoro | 1 | 20 | 11.05 |
| Peter Zipf | 2 | 186 | 45.00 |
| Oliver Soffke | 3 | 6 | 3.63 |
| Harald Klingbeil | 4 | 21 | 4.40 |
| Martin Kumm | 5 | 80 | 12.71 |
| Manfred Glesner | 6 | 1121 | 255.04 |