| An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications | 10 | 0.60 | 2014 |
| High speed low complexity FPGA-based FIR filters using pipelined adder graphs | 13 | 0.98 | 2011 |
| Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes | 6 | 0.77 | 2009 |
| On the design of reconfigurable multipliers for integer and Galois field multiplication | 5 | 0.58 | 2009 |
| Towards a unique FPGA-based identification circuit using process variations | 13 | 1.77 | 2009 |
| A decentralised task mapping approach for homogeneous multiprocessor network-on-chips | 12 | 0.55 | 2009 |
| Generation of Synthetic Floating-Point benchmark circuits | 0 | 0.34 | 2009 |
| Coarse-grained reconfiguration | 0 | 0.34 | 2008 |
| A scalable reconfiguration mechanism for fast dynamic reconfiguration | 3 | 0.52 | 2008 |
| Application-specific reconfigurable processors | 0 | 0.34 | 2008 |
| Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II | 0 | 0.34 | 2008 |
| An area-efficient FPGA realisation of a codebook-based image compression method | 0 | 0.34 | 2008 |
| Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. | 0 | 0.34 | 2007 |
| A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks | 3 | 0.46 | 2007 |
| On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication | 0 | 0.34 | 2007 |
| A Power Estimation Model For An Fpga-Based Softcore Processor | 2 | 0.39 | 2007 |
| Dynamically Reconfigurable Computing For Wireless Communication Systems | 0 | 0.34 | 2007 |
| A Customizable LEON2-Based VLIW Processor | 0 | 0.34 | 2007 |
| A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits | 0 | 0.34 | 2006 |
| Multitasking Support for Dynamically Reconfig Urable Systems | 1 | 0.52 | 2006 |
| Implementation of Realtime and Highspeed Phase Detector on FPGA | 4 | 0.78 | 2006 |
| Design Concepts for a Dynamically ReconfigurableWireless Sensor Node | 5 | 0.65 | 2006 |
| A metric for the energy-efficiency of dynamically reconfigurable systems | 1 | 0.40 | 2006 |
| Eine Scheduling Heuristik zur Minimierung der Verlustleistung. | 0 | 0.34 | 2006 |
| A Concept for a Profile-based Dynamic Reconfiguration Mechanism | 0 | 0.34 | 2006 |
| Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model | 0 | 0.34 | 2005 |
| Functional modeling techniques for a wireless LAN OFDM transceiver | 0 | 0.34 | 2005 |
| Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks | 1 | 0.36 | 2005 |
| A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture | 0 | 0.34 | 2004 |
| IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter | 0 | 0.34 | 2004 |
| Reconfigurable platforms for ubiquitous computing | 4 | 0.44 | 2004 |
| Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing | 5 | 0.55 | 2004 |
| An Asynchronous Switch Implmentation for Systems-on-a-Chip. | 0 | 0.34 | 2004 |
| A switch architecture and signal synchronization for GALS system-on-chips | 3 | 0.52 | 2004 |
| Dynamic Power Optimization Of The Trace-Back Process For The Viterbi Algorithm | 2 | 0.43 | 2004 |
| The XPP Architecture and Its Co-simulation Within the Simulink Environment | 13 | 1.09 | 2004 |
| Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. | 1 | 0.40 | 2004 |
| Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures | 0 | 0.34 | 2003 |
| An Integrated Model Bridging the Gap between Technology and Economy | 0 | 0.34 | 2003 |
| A hierarchical generic approach for on-chip communication, testing and debugging of SoCs | 4 | 0.49 | 2003 |
| A granularity-based classification model for systems-on-a-chip | 0 | 0.34 | 2003 |
| IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003 | 69 | 23.23 | 2003 |
| An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders | 3 | 0.47 | 2003 |
| Fly - A Modifiable Hardware Compiler | 2 | 0.59 | 2002 |
| Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension | 1 | 0.36 | 2002 |
| Integration und Fehlertoleranz im Codesign. | 0 | 0.34 | 2000 |
