Paper Info
Title
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy
Abstract
In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. There, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, we consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm.
Year
DOI
Venue
2006
10.1109/ASAP.2006.46
ASAP
Keywords
Field
DocType
minimum cost,partitioning method,processor arrays,new mapping approach,edge detection algorithm,optimization problem,efficient usage,sink pes,compute-intensive algorithm,inner schedule,significant algorithm acceleration,direct mapping,difference equations,acceleration,edge detection,cost function,parallel processing,topology,algorithm design and analysis,registers
Algorithm design,Computer science,Processor array,Edge detection,Parallel computing,Algorithm,Communication channel,Recurrence equations,Redundancy (engineering),Acceleration,Optimization problem
Conference
ISSN
ISBN
Citations 
2160-0511
0-7695-2682-9
2
PageRank 
References 
Authors
0.39
11
2
Name
Order
Citations
PageRank
Sebastian Siegel1294.16
Renate Merker215920.59