Massively Parallel Processor Architectures: A Co-design Approach | 1 | 0.36 | 2007 |
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels | 0 | 0.34 | 2006 |
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy | 2 | 0.39 | 2006 |
Efficient realization of data dependencies in algorithm partitioning under resource constraints | 0 | 0.34 | 2006 |
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching | 5 | 0.60 | 2005 |
Co-Design of Massively Parallel Embedded Processor Architectures | 9 | 0.67 | 2005 |
A Parallel Hardware-Software System for Signal Processing Algorithms | 0 | 0.34 | 2004 |
Optimized Data-Reuse in Processor Arrays | 6 | 0.57 | 2004 |
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays | 6 | 0.55 | 2004 |