Name
Title | ||
|---|---|---|
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs |
Abstract | ||
|---|---|---|
This paper presents a new generic system architecture and design methodology for the design, debugging and testing of complex
systems-on-chip (SoC). Starting from a hierarchical generic system architecture, platforms for dedicated application scenarios
will be customized. In order to be able to handle very complex submicron designs, the system is based on a globally asynchronous
and locally synchronous (GALS) concept. The problem of the increasing functionality versus outer access capabilities ratio
is faced by novel embedded and combined debugging and test structures. The integration of debugging possibilities is essential
for an efficient co-design of SoC integrated hardware and software, especially for systems with integrated reconfigurable
hardware parts.
|
Year | DOI | Venue |
|---|---|---|
2003 | 10.1007/0-387-33403-3_3 | VLSI-SOC |
Keywords | DocType | Citations |
built-in self test,sihcon debug,networks-on-chip | Conference | 4 |
PageRank | References | Authors |
0.49 | 7 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thomas Hollstein | 1 | 161 | 21.88 |
| Ralf Ludewig | 2 | 12 | 3.56 |
| Christoph Mager | 3 | 4 | 0.49 |
| Peter Zipf | 4 | 186 | 45.00 |
| Manfred Glesner | 5 | 1121 | 255.04 |
| Manfred Glesner | 6 | 182 | 36.92 |