Name
Abstract | ||
|---|---|---|
This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietisy/e91-d.3.690 | IEICE Transactions |
Keywords | Field | DocType |
stuck-at test tools,stuck-at fault,fault simulation,test generation process,logic level fault simulation,fault efficiency,proposed fault simulation,test pattern,test generation,stuck-at test generator,fault coverage,design for testability | Design for testing,Fault coverage,Computer science,Artificial intelligence,Stuck-at fault,Automatic test pattern generation,Test method,Pattern recognition,Logic simulation,Test compression,Reliability engineering,Fault indicator,Embedded system | Journal |
Volume | Issue | ISSN |
E91-D | 3 | 1745-1361 |
Citations | PageRank | References |
1 | 0.37 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Kewal K. Saluja | 2 | 1483 | 141.49 |
| Hiroshi Takahashi | 3 | 148 | 24.32 |
| Shin-ya Kobayashi | 4 | 38 | 8.60 |
| Yuzo Takamatsu | 5 | 150 | 27.40 |