Paper Info
Title
A 1.62 Gb/s–2.7 Gb/s Referenceless Transceiver for DisplayPort v1.1a With Weighted Phase and Frequency Detection
Abstract
This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.
Year
DOI
Venue
2013
10.1109/TCSI.2012.2215779
IEEE Transactions on Circuits and Systems I-regular Papers
Keywords
Field
DocType
cmos process,phase detection,transceivers,phase and frequency detection,voltage 1.2 v,bit rate 1.62 gbit/s to 2.7 gbit/s,jitter,referenceless transceiver,receiver,weighted phase,weighted pfd,encoding,ber,pll,clock and data recovery,phase locked loops,deserializer,serializer,frequency detection,referenceless transceiver architecture,cmos digital integrated circuits,ansi decoder,scrambler,ansi encoder,single loop referenceless cdr,error statistics,decoding,clock and data recovery circuits,displayport v1.1a
Phase-locked loop,Transmitter,Transceiver,DisplayPort,Serializer,Electronic engineering,Encoder,Phase detector,Jitter,Mathematics
Journal
Volume
Issue
ISSN
60
2
1549-8328
Citations 
PageRank 
References 
12
0.80
8
Authors
6
Name
Order
Citations
PageRank
Junyoung Song14011.42
Inhwa Jung27011.23
Minyoung Song3406.89
Young-Ho Kwak4446.75
Sewook Hwang54110.43
Chulwoo Kim639774.58