Paper Info
Title
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit.
Abstract
An adiabatic 64-kb SRAM circuit with shared reading and writing ports was designed, which enables gradual charging and discharging while maintaining a large VDD so that the problems of V-T variation and electromigration in the nanocircuit can be solved. In the writing mode, the voltage of the memory cell ground line is increased to VDD/2 gradually, and the nMOSFET is turned off so that the memory cell ground line is set in a high-impedance state. Data can then be written easily by decreasing the voltage of one bit line adiabatically, while the voltage of the other bit line remains high. For reading, using the shared reading port, the voltage swing of the global bit-line can be decreased to VDD/4 so that the problems of electromigration can be solved. The reading method enables a gradual current flow in the memory cell. We designed the cell layout and confirmed that the number of transistors in the cell is quasi-six. In addition, two types of new step voltage circuits with tank capacitors are proposed. One is for producing the memory cell ground line voltage and the other for charging the word line voltage adiabatically. Spontaneous step voltage formation is confirmed experimentally.
Year
DOI
Venue
2010
10.1109/ISCAS.2010.5537144
ISCAS
Keywords
Field
DocType
computer architecture,layout,transistor,electromigration,transistors,writing,nanoelectronics,integrated circuit layout
Integrated circuit layout,Capacitor,Computer science,Voltage,Static random-access memory,Electronic engineering,MOSFET,Electronic circuit,Transistor,Electrical engineering,Memory cell
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-4244-5309-2
10
PageRank 
References 
Authors
0.74
3
8
Name
Order
Citations
PageRank
Shunji Nakata16613.07
Hirotsugu Suzuki2241.97
Ryota Honda3202.34
Takahito Kusumoto4181.97
Shin'ichiro Mutoh5647.01
Hiroshi Makino6455.83
Masayuki Miyama79820.67
Yoshio Matsuda86211.85