Abstract | ||
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In this paper, we explore the challenges in scaling on-chip networks towards kilo-core processors. Current low-radix topologies optimize for fast local communication, but do not scale well to kilo-core systems because of the large number of routers required. These increase both power and hop count. In contrast, symmetric high-radix topologies optimize for global communication with fewer hop counts, but degrade local communication with their large, slow routers. |
Year | DOI | Venue |
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2013 | 10.1109/HPCA.2013.6522344 | HPCA |
Keywords | Field | DocType |
fast local communication,asymmetric high-radix topology,degrade local communication,kilo-core processor,slow routers,large number,fewer hop count,on-chip network,global communication,current low-radix topologies optimize,hop count,network routing,integrated circuit design,network topology,system on chip | System on a chip,Computer science,Clos network,Latency (engineering),Wire speed,Parallel computing,Real-time computing,Network topology,Integrated circuit design,Interconnection,Scalability | Conference |
ISSN | ISBN | Citations |
1530-0897 | 978-1-4673-5585-8 | 11 |
PageRank | References | Authors |
0.49 | 23 | 8 |
Name | Order | Citations | PageRank |
---|---|---|---|
Nilmini Abeyratne | 1 | 14 | 2.00 |
Reetuparna Das | 2 | 1117 | 47.07 |
Qingkun Li | 3 | 24 | 1.43 |
Korey Sewell | 4 | 925 | 28.32 |
Bharan Giridhar | 5 | 76 | 4.93 |
Ronald G. Dreslinski | 6 | 1258 | 81.02 |
David Blaauw | 7 | 8916 | 823.47 |
Trevor Mudge | 8 | 6139 | 659.74 |