| Multi-Layer In-Memory Processing | 0 | 0.34 | 2022 |
| Special Issue on In-Memory Computing | 1 | 0.34 | 2022 |
| A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array | 0 | 0.34 | 2021 |
| Cache Compression with Efficient in-SRAM Data Comparison | 0 | 0.34 | 2021 |
| MyML: User-Driven Machine Learning | 0 | 0.34 | 2021 |
| Accelerated Seeding for Genome Sequence Alignment with Enumerated Radix Trees | 0 | 0.34 | 2021 |
| GenomicsBench: A Benchmark Suite for Genomics | 0 | 0.34 | 2021 |
| SquiggleFilter: An Accelerator for Portable Virus Detection | 0 | 0.34 | 2021 |
| Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs | 1 | 0.35 | 2021 |
| Seesaw: End-to-end Dynamic Sensing for IoT using Machine Learning | 0 | 0.34 | 2020 |
| Neksus: An Interconnect for Heterogeneous System-In-Package Architectures | 1 | 0.39 | 2020 |
| SeedEx: A Genome Sequencing Accelerator for Optimal Alignments in Subminimal Space | 0 | 0.34 | 2020 |
| MARTINI: Memory Access Traces to Detect Attacks | 0 | 0.34 | 2020 |
| A 2.46M reads/s Genome Sequencing Accelerator using a 625 Processing-Element Array | 0 | 0.34 | 2020 |
| A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing | 13 | 0.65 | 2020 |
| TF-Net: Deploying Sub-Byte Deep Neural Networks on Microcontrollers | 1 | 0.37 | 2019 |
| 14.2 A Compute SRAM with Bit-Serial Integer/Floating-Point Operations for Programmable In-Memory Vector Acceleration | 5 | 0.49 | 2019 |
| Duality cache for data parallel acceleration | 14 | 0.58 | 2019 |
| Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks | 8 | 0.42 | 2019 |
| Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks. | 29 | 0.71 | 2018 |
| GenAx: A Genome Sequencing Accelerator. | 5 | 0.38 | 2018 |
| ASPEN - A Scalable In-SRAM Architecture for Pushdown Automata. | 0 | 0.34 | 2018 |
| In-Memory Data Parallel Processor. | 24 | 0.75 | 2018 |
| Cache Automaton: Repurposing Caches for Automata Processing | 1 | 0.35 | 2017 |
| Parallel Automata Processor. | 2 | 0.35 | 2017 |
| Cold Boot Attacks are Still Hot: Security Analysis of Memory Scramblers in Modern Processors | 4 | 0.41 | 2017 |
| Mirage cores: the illusion of many out-of-order cores using in-order hardware. | 2 | 0.36 | 2017 |
| In-memory Data Flow Processor | 1 | 0.35 | 2017 |
| Scalpel: Customizing DNN Pruning to the Underlying Hardware Parallelism. | 30 | 0.81 | 2017 |
| Compute Caches. | 0 | 0.34 | 2017 |
| Blurring the Lines between Memory and Computation. | 0 | 0.34 | 2017 |
| Cache automaton. | 14 | 0.58 | 2017 |
| ANVIL: Software-Based Protection Against Next-Generation Rowhammer Attacks. | 29 | 1.07 | 2016 |
| Exploring Specialized Near-Memory Processing For Data Intensive Operations | 5 | 0.39 | 2016 |
| Achieving both High Energy Efficiency and High Performance in On-Chip Communication using Hierarchical Rings with Deflection Routing. | 0 | 0.34 | 2016 |
| A case for hierarchical rings with deflection routing: An energy-efficient on-chip communication substrate. | 0 | 0.34 | 2016 |
| Exploring Fine-Grained Heterogeneity with Composite Cores | 3 | 0.38 | 2016 |
| Getting in control of your control flow with control-data isolation | 4 | 0.42 | 2015 |
| Locking down insecure indirection with hardware-based control-data isolation | 2 | 0.37 | 2015 |
| DynaMOS: dynamic schedule migration for heterogeneous cores | 6 | 0.49 | 2015 |
| Heterogeneous microarchitectures trump voltage scaling for low-power cores | 17 | 0.64 | 2014 |
| VIX: Virtual Input Crossbar for Efficient Switch Allocation | 6 | 0.47 | 2014 |
| Power-Aware NoCs through Routing and Topology Reconfiguration | 25 | 0.82 | 2014 |
| Design and Evaluation of Hierarchical Rings with Deflection Routing | 10 | 0.52 | 2014 |
| Hi-Rise: A High-Radix Switch for 3D Integration with Single-Cycle Arbitration | 6 | 0.48 | 2014 |
| Quality-of-Service for a High-Radix Switch | 0 | 0.34 | 2014 |
| Scaling towards kilo-core processors with asymmetric high-radix topologies | 11 | 0.49 | 2013 |
| Trace based phase prediction for tightly-coupled heterogeneous cores | 22 | 0.74 | 2013 |
| Catnap: energy proportional multiple network-on-chip | 64 | 1.55 | 2013 |
| Application-to-core mapping policies to reduce memory system interference in multi-core systems | 40 | 0.82 | 2013 |
