Name
Abstract | ||
|---|---|---|
In an SMT processor an increasing number of register contexts of a thread requires a large number of physical registers. Moreover, a physical register file in an SMT processor requires more ports for the increasing number of execution units, which causes significant growth of area, access time and power consumption of a register file. These problems are significant hurdles to implement an SMT processor which executes the more number of threads with the more execution units. Especially, growth of access time of a register file has a large impact on performance. In this paper, we propose a strategy of dividing a physical register file into some banks and dynamic allocation of them to threads in order to reduce the access time of a register file. We have accomplished reduction in access time of a register file up to 60% without growth of area by using the proposed strategy. On the contrary, IPC degradation can be limited up to 6% by this strategy. |
Year | Venue | Keywords |
|---|---|---|
2004 | PDPTA '04: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS 1-3 | SMT, register bank, register access delay, dynamic allocation |
Field | DocType | Citations |
Register allocation,Computer science,Parallel computing,Processor register,Operating system | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Norito Kato | 1 | 3 | 1.19 |
| Masanori Yamato | 2 | 3 | 1.19 |
| Osamu Tujimoto | 3 | 0 | 0.34 |
| Mikiko Sato | 4 | 22 | 11.53 |
| Koichi Sasada | 5 | 9 | 2.50 |
| Kaname Uchikura | 6 | 5 | 1.95 |
| Mitaro Namiki | 7 | 97 | 20.69 |
| Hironori Nakajo | 8 | 69 | 20.66 |