Title
Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package
Abstract
This paper reports the design, assembly and reliability assessment of 21×21mm2 Cu/low-k flip chip (65nm node) with 150μm bump pitch and high bump density. To reduce the stress from the solder bump pad to low-k layers, Metal Redistribution Layer (RDL) and Polymer Encapsulated Dicing Lane (PEDL) are applied to the Cu/low-k wafer. Lead-free Sn2.5Ag, high-lead Pb5Sn and Cu-post/Sn37Pb bumps are evaluated as the first-level interconnects. It is found that the flip chip assembly of high-lead bumped test vehicle requires the right choice of flux and good alignment between the high-lead solder bumps and substrate pre-solder alloy to ensure proper solder bump and substrate pre-solder alloy wetting. Joint Electron Device Engineering Council (JEDEC) standard reliability is performed on the test vehicle with different first-level interconnects, underfill materials and PEDL.
Year
DOI
Venue
2010
10.1016/j.microrel.2010.03.010
Microelectronics Reliability
Keywords
Field
DocType
chip,flip chip
Flip chip,Electronic packaging,Chip,Electronic engineering,Redistribution layer,Soldering,Thermal copper pillar bump,Engineering,Wafer dicing,Integrated circuit
Journal
Volume
Issue
ISSN
50
7
0026-2714
Citations 
PageRank 
References 
0
0.34
3
Authors
20