Name
Abstract | ||
|---|---|---|
The testability of a sequential circuit can be improved by controlling the cloclcs of individual storage elements during testing. We propose several clock control strategies derived from an analysis of the circuit, its S-graph structure, and its function. Through examples we show how the number of clocks afleets the circuit's testability. It is shown that if certain flip-flops (FFs)are scanned (or otherwise initialized), the remaining FFs can be controlled and initialized to any arbitrary state using the clock control. We derive a controllability graph and use it to assign clocks to FFs and to schedule the clocks to set the FFs to an arbitrary state during test. Our analysis of sequential benchmark circuits indicates that this could be an attractive schemefor combining partial scan with clock control. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/GLSV.1996.497635 | Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
clock control,s-graph structure,sequential circuit,improving circuit testability,arbitrary state,attractive schemefor,clock control strategy,remaining ffs,certain flip-flop,controllability graph,sequential benchmark circuit,sequential analysis,sequential circuits,circuit analysis,hardware,testability,computer science,benchmark testing | Testability,Sequential logic,Controllability,Computer science,Clock control,Real-time computing,Electronic engineering,Synchronous circuit,Clock skew,Electronic circuit,Asynchronous circuit | Conference |
ISSN | ISBN | Citations |
1066-1395 | 0-8186-7502-0 | 8 |
PageRank | References | Authors |
0.64 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kent L. Einspahr | 1 | 19 | 2.63 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Vishwani D. Agrawal | 3 | 3502 | 470.06 |