Name
Abstract | ||
|---|---|---|
Transistor sizing at layout level is necessary to improve the overall performance of integrated circuits. We present in this paper the definition and the validation of a sizing aid, P.Size, integrated in a flexible cell generator. Based on a local optimization defined through an explicit formulation of delays, this sizing aid can be used to optimize real data paths, under constraint, with few CPU time requirements. Validations, through comparison with a mathematical optimization procedure and an industrial optimizer, are given. |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/EURDAC.1992.246248 | EURO-DAC '92 Proceedings of the conference on European design automation |
Keywords | Field | DocType |
optimized design,sizing aid,local optimization,integrated circuit layout,central processing unit,fabrication,vlsi,design optimization,constraint optimization,optimal design,integrated circuit,robots | CPU time,Computer science,Circuit extraction,IC layout editor,Electronic engineering,Real-time computing,Sizing,Topology optimization,Physical design,Local search (optimization),Very-large-scale integration,Reliability engineering | Conference |
ISBN | Citations | PageRank |
0-8186-2780-8 | 1 | 0.67 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. Azemard | 1 | 104 | 14.17 |
| Bonzom, V. | 2 | 8 | 1.66 |
| Daniel Auvergne | 3 | 145 | 31.67 |