Name
Abstract | ||
|---|---|---|
This paper presents the design of a time-to-digital converter (TDC) suitable for a 3.5-GHz all-digital phase-lock loop (PLL). The converter is based on a digital bang-bang delay-lock loop, which allows constant resolution over process and temperatures spreads, avoids an off-chip filter and guarantees fast lock. The clock rate of the digital filter is scaled down by eight from the 3.5-GHz input to allow its implementation with standard cells. The occurrence of a limit cycle is analytically predicted and properly minimized, and its effect on the PLL phase noise is discussed. The circuit fabricated in 90-nm CMOS entails 16 delay stages, which lock to the input frequency in the 2.9-3.9-GHz range (limited by the available signal source). The delay of each TDC cell can be controlled with 50-fs step and the TDC time resolution is 16 ps at 3.9 GHz. The power consumption ranges between 8.1 and 16.5 mW, respectively. The limit-cycle-induced spur is below - 50 dBc. The area occupation is 0.032 mm2. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2009.2023945 | Circuits and Systems I: Regular Papers, IEEE Transactions |
Keywords | Field | DocType |
clock rate,delay lock loop,phase lock loop,cmos,bang bang control,temperature,chip,digital filter,phase noise,phase locked loops,digital filters,limit cycle,nanofabrication,cmos integrated circuits | Phase-locked loop,Bang–bang control,Digital filter,Control theory,Phase noise,CMOS,Electronic engineering,dBc,Time-to-digital converter,Mathematics,Clock rate | Journal |
Volume | Issue | ISSN |
57 | 3 | 1549-8328 |
Citations | PageRank | References |
20 | 1.60 | 12 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Marco Zanuso | 1 | 152 | 14.89 |
| Paolo Madoglio | 2 | 91 | 13.34 |
| Salvatore Levantino | 3 | 351 | 43.23 |
| Carlo Samori | 4 | 349 | 39.76 |
| Andrea L. Lacaita | 5 | 320 | 42.41 |