Name
Title | ||
|---|---|---|
Low Power Sram With Boost Driver Generating Pulsed Word Line Voltage For Sub-1v Operation |
Abstract | ||
|---|---|---|
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs. This paper presents a boosted word line voltage scheme, where an active body-biasing controlled boost transistor generates a pulsed word line voltage by capacitive coupling only when accessed. Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of V-th variation on performance even at ultra low supply voltage less than 0.5 V. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.4304/jcp.3.5.34-40 | JOURNAL OF COMPUTERS |
Keywords | Field | DocType |
SRAM, Circuit methodology, Low power, Low voltage, PD-SOI, V-th variation | Pattern recognition,Access time,Computer science,Voltage,Static random-access memory,Real-time computing,Process variation,Low voltage,Artificial intelligence,Transistor,Electrical engineering,Capacitive coupling | Journal |
Volume | Issue | ISSN |
3 | 5 | 1796-203X |
Citations | PageRank | References |
6 | 0.86 | 1 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masaaki Iijima | 1 | 13 | 4.68 |
| Kayoko Seto | 2 | 6 | 1.54 |
| Masahiro Numa | 3 | 82 | 20.87 |
| Akira Tada | 4 | 14 | 4.40 |
| Takashi Ipposhi | 5 | 13 | 5.97 |