Name
Abstract | ||
|---|---|---|
In a random testing environment, a significant amount ofenergy is wasted in the LFSR and in the CUT by uselesspatterns that do not contribute to fault dropping. Anothermajor source of energy drainage is the loss due to randomswitching activity in the CUT and in the scan path betweenapplications of two successive vectors. In this work, a newbuilt-in self-test (BIST) scheme for scan-based circuits isproposed for reducing such energy consumption. Amapping logic is designed which modifies the statetransitions of the LFSR such that only the useful vectorsare generated according to a desired sequence. Further, itreduces test application time without affecting faultcoverage. Experimental results on ISCAS-89 benchmarkcircuits reveal a significant amount of energy savings inthe LFSR during random testing. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ICVD.2003.1183191 | VLSI Design |
Keywords | Field | DocType |
amapping logic,low-energy bist design,scan-based logic circuits,energy consumption,iscas-89 benchmarkcircuits,random testing,random testing environment,anothermajor source,significant amount,energy savings inthe lfsr,energy drainage,significant amount ofenergy,combinational circuits,state transition,vlsi,fault coverage | Logic gate,Random testing,Fault coverage,Computer science,Algorithm,Real-time computing,Electronic engineering,Combinational logic,Electronic circuit,Energy consumption,Very-large-scale integration,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7695-1868-0 | 8 | 0.56 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bhargab B. Bhattacharya | 1 | 848 | 118.02 |
| Sharad C. Seth | 2 | 671 | 93.61 |
| Sheng Zhang | 3 | 21 | 1.50 |