Name
Title | ||
|---|---|---|
7t Sram Enabling Low-Energy Instantaneous Block Copy And Its Application To Transactional Memory |
Abstract | ||
|---|---|---|
This paper proposes 7T SRAM which realizes block-level simultaneous copying feature. The proposed SRAM can be used for data transfer between local memories such as checkpoint data storage and transactional memory. The 1-Mb SRAM is comprised of 32-kb blocks, in which 16-kb data can be copied in 33.3 ns at 1.2 V. The proposed scheme reduces energy consumption in copying by 92.7% compared to the conventional read-modify-write manner. By applying the proposed scheme to transactional memory, the number of write back cycles is possibly reduced by 98.7% compared with the conventional memory system. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transfun.E94.A.2693 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
SRAM DMA, transactional memory, checkpoint and recovery, multi-core processor | Sense amplifier,Computer science,Computer data storage,Static random-access memory,Transactional memory,Universal memory,Conventional memory,Multi-core processor,Energy consumption,Embedded system | Journal |
Volume | Issue | ISSN |
E94A | 12 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 8 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shunsuke Okumura | 1 | 63 | 12.54 |
| Yuki Kagiyama | 2 | 0 | 0.34 |
| Yohei Nakata | 3 | 29 | 5.55 |
| Shusuke Yoshimoto | 4 | 30 | 12.56 |
| Hiroshi Kawaguchi | 5 | 37 | 21.08 |
| Masahiko Yoshimoto | 6 | 0 | 0.34 |