Name
Abstract | ||
|---|---|---|
Turbo decoders inherently require large hardware for VLSI implementation as a large amount of memory is required to store incoming data and intermediate computation results. Design of highly efficient Turbo decoders requires reduction of hardware size and power consumption. In this paper, finite precision effects on the performance of Turbo decoders are analyzed and the optimal word lengths of variables are determined considering tradeoffs between the performance and the hardware cost. It is shown that the performance degradation from the infinite precision is negligible if 4 bits are used for received bits and 6 bits for the extrinsic information. The state metrics normalization method suitable for Turbo decoders is also discussed. This method requires small amount of hardware and its speed does not depend on the number of states. Furthermore, we propose a novel adaptive decoding approach which does not lead to performance degradation and is suitable for VLSI implementation. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1023/A:1012283413624 | Journal of Signal Processing Systems |
Keywords | Field | DocType |
VLSI implementation,turbo codes,adaptive decoding,MAP algorithm | Turbo,Normalization (statistics),Computer science,Serial concatenated convolutional codes,Turbo code,Real-time computing,Theoretical computer science,Turbo equalizer,Decoding methods,Very-large-scale integration,Difference-map algorithm | Journal |
Volume | Issue | ISSN |
29 | 3 | 0922-5773 |
Citations | PageRank | References |
4 | 0.49 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhongfeng Wang | 1 | 7 | 1.24 |
| H. Suzuki | 2 | 238 | 31.31 |
| keshab k parhi | 3 | 3235 | 369.07 |