H. Suzuki - Citegraph

Author Info

Name	Affiliation	Papers
H. SUZUKI	Department of Precision Machinery Engineering, Graduate School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan	34
Collaborators	Citations	PageRank
81	238	31.31
Referers	Referees	References
525	278	146

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100525

Publications (34 rows)

Collaborators (81 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
High Performance Oam Communication Exploiting Port-Azimuth Effect Of Loop Antennas	0	0.34	2019
Fabrication Of Inp/Ingaas Dhbts With Buried Sio2 Wires	0	0.34	2011
Input design for hybrid system identification for accurate estimation of submodel regions	1	0.35	2011
Basic examination concerning multiagent cooperation with entrainment	0	0.34	2009
Discrimination of similar characters with a nonlinear compound discriminant function	1	0.41	2007
Optimal input design for system identification in the presence of undermodeling	0	0.34	2007
Adaptive MAP receiver via the EM algorithm and message passings for MIMO-OFDM mobile communications	27	1.28	2006
Developing and analyzing geographical content display system by using RFID	0	0.34	2006
String-Like Occluding Region Extraction for Background Restoration	8	0.56	2006
Are We Making Progress? -An Analysis of NTCIR QAC1 and 2	0	0.34	2004
Enhanced Multi-Antenna Technologies on OFDM for Future Mobile Communication Systems	0	0.34	2003
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders	4	0.49	2001
Robust photonic transport network implementation with optical cross connect systems	19	1.71	2000
A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder	32	2.33	2000
Efficient approaches to improving performance of VLSI SOVA-based turbo decoders	3	0.54	2000
Slotted ALOHA mobile packet communication systems with multiuser detection in a base station	14	0.70	2000
Prototype AWA: design and implementation of a high speed ATM wireless access system using 25 GHz band	1	0.36	1999
Shape Error Evaluation Method Of Free-Form Surfaces	6	0.64	1999
Low-power bit-serial Viterbi decoder for next generation wide-band CDMA systems.	2	0.41	1999
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]	4	1.10	1997
Solving regional constraints in components layout design based on geometric gadgets	2	0.41	1997
An NC parallel algorithm for edge-coloring series-parallel multigraphs	2	0.40	1997
Shortest Non-Crossing Rectilinear Paths In Plane Regions	0	0.34	1997
A linear algorithm for edge-coloring series-parallel multigraphs	10	0.84	1996
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture	34	4.26	1996
Finding a Shortest Pair of Paths on the Plane with Obstacles and Crossing Areas	2	0.42	1995
Sequential and parallel algorithms for edge-coloring series-parallel multigraphs	6	0.57	1993
A Cnn Handwritten Character Recognizer	4	0.65	1992
Algorithms for routing around a rectangle	42	6.83	1992
Fast carrier-tracking coherent detection with dual-mode carrier recovery circuit for digital land mobile radio transmission	7	1.25	1989
Synchronous composite packet switching—a switching architecture for broadband ISDN	2	0.38	1987
Synchronous Composite Packet Switching for Broadband ISDN	1	0.38	1986
Multicommodity flows in planar undirected graphs and shortest paths	4	0.99	1985
A digital signal processor module architecture and its implementation using VLSIs	0	0.34	1984