Name
Abstract | ||
|---|---|---|
This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS'89 benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/DELTA.2002.994665 | Christchurch |
Keywords | Field | DocType |
original fault coverage,test vector,cmos circuits,power dissipation,cmos sequential circuit,logic simulation,modifying test vectors,fault simulation,average number,signal transition gate,maximum number,capacitance,fault coverage,fault detection,sequential circuits,sequential analysis,benchmark testing | Test vector,Sequential logic,Fault coverage,Dissipation,Fault detection and isolation,Signal transition,Computer science,Electronic engineering,CMOS,Real-time computing,Logic simulation | Conference |
ISBN | Citations | PageRank |
0-7695-1453-7 | 1 | 0.37 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Shin-ya Kobayashi | 2 | 38 | 8.60 |
| Yuzo Takamatsu | 3 | 150 | 27.40 |