Paper Info
Title
A Framework For Effective Exploitation Of Partial Reconfiguration In Dataflow Computing
Abstract
The exploitation of high-performance architectures based on reconfigurable hardware to build power efficient supercomputing clusters is becoming more and more common. Indeed, large speedups have already been demonstrated in several high-performance computing (HPC) applications. On the other hand, partial reconfiguration (PR) has the potential to further increase performance and power efficiency in many applications; however, there is currently very limited support for transforming a traditional design into a reconfigurable one. In this work, we introduce a design methodology for PR designs that combines application analysis, partitioning, mapping and scheduling, and supports fast exploration of various design options. These steps are integrated in an automated toolchain which allows a designer to implement reconfigurable designs with simple guidance through a graphical interface. We demonstrate our approach by applying the methodology to an image processing application, implementing the proposed design on a Maxeler MaxWorkstation.
Year
DOI
Venue
2013
10.1109/ReCoSoC.2013.6581535
2013 8TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC)
Keywords
Field
DocType
graphical interface,hpc,digital signal processing,high performance computing,design methodology,image processing,field programmable gate arrays,parallel processing,reconfigurable hardware,graphical user interfaces,throughput,power efficiency,hardware
Computer architecture,Supercomputer,Computer science,Scheduling (computing),Parallel computing,Design methods,Dataflow,Graphical user interface,Toolchain,Control reconfiguration,Reconfigurable computing,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
9
Authors
6
Name
Order
Citations
PageRank
Riccardo Cattaneo1579.14
Xinyu Niu213523.16
Christian Pilato332932.19
Tobias Becker419523.79
Wayne Luk53752438.09
Marco D. Santambrogio677191.15