Paper Info
Title
Architectural Exploration and Optimization for Counter Based Hardware Address Generation
Abstract
A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.
Year
DOI
Venue
1997
10.1109/EDTC.1997.582373
ED&TC
Keywords
Field
DocType
resulting area figure,hardware address generation,address generation unit,early stage,area cost,design process,architectural decision,automated system level technique,architectural exploration,large impact,different architectural alternative,real time,signal generators,signal processing,bandwidth,system architecture,constraint optimization,architecture,design,memory management,hardware,distributed memory,real time systems,optimization
Signal processing,Architecture,Computer architecture,Computer science,Electronic engineering,Real-time computing,Bandwidth (signal processing),Memory management,Engineering design process,Architectural pattern,Memory architecture,Constrained optimization
Conference
ISSN
ISBN
Citations 
1066-1409
0-8186-7786-4
6
PageRank 
References 
Authors
0.54
10
4
Name
Order
Citations
PageRank
M. Miranda114411.00
M. Kaspar260.54
F. Catthoor389783.95
H. De Man449083.62