Name
Abstract | ||
|---|---|---|
The first path implicit and exact non-robust path delay fault grading technique for non-scan sequential circuits is presented. Non enumerative exact coverage is obtained, by allowing any latched error representing a delayed transition to propagate to a primary output with thesupport of other potentially latched errors. The generalized error propagation is done by symbolic simulation. Appropriate data structures for function manipulation are used. The advantage of the proposed method is demonstrated experimentally with consistent improvement in coverage over an existing pessimistic heuristic despite enforced bounds onthe memory requirements. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/DATE.2005.179 | DATE |
Keywords | Field | DocType |
sequential circuits,logic simulation,data structure,manufacturing,logic design,sequential analysis,propagation delay,automatic test pattern generation,generalization error,robustness,spc,data structures | Automatic test pattern generation,Symbolic simulation,Sequential logic,Propagation of uncertainty,Propagation delay,Computer science,Real-time computing,Robustness (computer science),Logic simulation,Fault grading | Conference |
ISSN | ISBN | Citations |
1530-1591 | 0-7695-2288-2 | 2 |
PageRank | References | Authors |
0.37 | 9 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahilchi Milir Vaseekar Kumar | 1 | 2 | 0.71 |
| Spyros Tragoudas | 2 | 625 | 88.87 |
| Sreejit Chakravarty | 3 | 518 | 57.46 |
| R. Jayabharathi | 4 | 12 | 4.42 |