Name
Abstract | ||
|---|---|---|
For recent VLSIs designe for low power, reduction ofpower dissipation during test is one of the most impor-tant problems.This paper presents a metho to reducepower dissipation during test for sequential circuits.The goal is to obtain test vectors for sequential circuitsthat achieve low power dissipation.In our method,testvectors generate by ATPG are given and they are im-prove to reduce power dissipation without losing theoriginal stuck-at fault coverage.Due to the correlationbetween power dissipation and the number of transitiongates, the number of transition gates is evaluate foreach test vector during modification of test vectors.Inorder to keep the original fault coverage, logic simula-tion and fault simulation are performed, every time atest vector is modified.The effectiveness of our methodis shown by experimental results for ISCAS '89 bench-mark circuits. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/ATS.2002.1181732 | Asian Test Symposium |
Keywords | Field | DocType |
sequential circuits,original fault coverage,low power,reduction ofpower dissipation,test vector,reduce power dissipation,power dissipation,low power dissipation,correlationbetween power dissipation,foreach test vector,theoriginal stuck-at fault coverage,fault simulation,logic simulation,vlsi design,low power electronics,fault coverage,automatic test pattern generation,vlsi | Test vector,Automatic test pattern generation,Sequential logic,Fault coverage,Computer science,Dissipation,Electronic engineering,Real-time computing,Logic simulation,Test compression,Low-power electronics | Conference |
ISBN | Citations | PageRank |
0-7695-1825-7 | 0 | 0.34 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Shin-ya Kobayashi | 2 | 38 | 8.60 |
| Yuzo Takamatsu | 3 | 150 | 27.40 |