Paper Info
Title
High-Level Synthesis of Scalable Architectures for IIR Filters Using Multichip Modules
Abstract
We present a new technique for the high-level synthesis of scalable MCM-based architectures implementing infinite-impulse response(IIR) filters. Our technique is based on the regular schedules, a class of parallel schedules for computing mth-order IIR filters. The simplicity of the regular schedules facilitates characterization of their inter-processor communications, which is generally difficult to express for parallel algorithms. The characterization of inter-processor communications of the regular schedules enables us to generate instruction-level behavior of the design that can be easily mapped onto MCM-based architectures. We illustrate this mapping of the regular schedules onto an MCM-based architecture by designing a special-purpose processor for the fifth-order elliptic wave filter. Our design yields a scalable performance measured in the filter's sample rate, which is not known to have been achieved by previously published designs. This work differs significantly from "traditional" high-level synthesis techniques in its emphasis on synthesizing scalable, high-performance multichip designs.
Year
DOI
Venue
1993
10.1109/DAC.1993.203971
DAC
Keywords
Field
DocType
scalable architecture,high-level synthesis,multichip module,signal processing,chip,computer architecture,concurrent computing,difference equations,high level synthesis,parallel processing,iir filter,infinite impulse response,parallel algorithm
Signal processing,Computer science,Parallel algorithm,Infinite impulse response,High-level synthesis,Sampling (signal processing),Real-time computing,Electronic engineering,Schedule,Concurrent computing,Scalability
Conference
ISSN
ISBN
Citations 
0738-100X
0-89791-577-1
2
PageRank 
References 
Authors
0.39
12
4
Name
Order
Citations
PageRank
Haigeng Wang1687.39
Nikil Dutt24960421.49
Alexandru Nicolau32265307.74
Kai-Yeung Sunny Siu4996110.51