Paper Info
Title
Width minimization in the Single-Electron Transistor array synthesis
Abstract
Power consumption has become one of the primary challenges to meet the Moore's law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore's law due to its ultra-low power consumption during operation. Prior work has proposed an automated mapping approach for SET arrays which focuses on minimizing the number of hexagons in an SET array. However, the area of an SET array is more related to the width. Consequently, in this work, we propose an approach for width minimization of the SET arrays. The experimental results show that the proposed approach saves 26% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks while spending similar CPU time.
Year
DOI
Venue
2014
10.7873/DATE.2014.135
DATE
Keywords
Field
DocType
automated mapping approach,iwls 2005 benchmarks,set array,single-electron transistor,power consumption,binary decision diagrams,prior work,width minimization,ultra-low power consumption,single-electron transistor array synthesis,moores law,single electron transistors,mcnc,primary challenge,benchmark testing,boolean functions,nist
Coulomb blockade,CPU time,Computer science,Electronic engineering,Pattern synthesis,Minification,Transistor,Electrical engineering,Power consumption
Conference
ISSN
Citations 
PageRank 
1530-1591
6
0.55
References 
Authors
8
7
Name
Order
Citations
PageRank
Chian-Wei Liu1121.34
Chang-En Chiang2191.33
Ching-Yi Huang35810.06
Wang Chun-Yao425136.08
Yung-Chih Chen541339.89
Suman Datta641551.93
Narayanan Vijaykrishnan76955524.60