Ching-Yi Huang - Citegraph

Author Info

Name	Affiliation	Papers
CHING-YI HUANG	National Tsing Hua University, Hsinchu, Taiwan, R. O. C.	25
Collaborators	Citations	PageRank
44	58	10.06
Referers	Referees	References
93	341	275

Search Limit

100341

Publications (25 rows)

Collaborators (44 rows)

Referers (93 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited Talk	0	0.34	2020
2019 CAD Contest: Logic Regression on High Dimensional Boolean Space	1	0.37	2019
Using range-equivalent circuits for facilitating bounded sequential equivalence checking	0	0.34	2018
ICCAD-2017 CAD contest in resource-aware patch generation.	0	0.34	2017
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays	1	0.36	2017
Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.	1	0.35	2016
Area-Aware Decomposition for Single-Electron Transistor Arrays.	2	0.38	2016
Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.	3	0.39	2016
MajorSat: A SAT solver to majority logic	0	0.34	2016
An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.	3	0.39	2016
Synthesis and verification of cyclic combinational circuits	1	0.38	2015
Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits	1	0.37	2015
Using structural relations for checking combinationality of cyclic circuits	1	0.37	2015
A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays	3	0.40	2015
Synthesis for Width Minimization in the Single-Electron Transistor Array	4	0.42	2015
Rewiring for threshold logic circuit minimization	2	0.40	2014
Width minimization in the Single-Electron Transistor array synthesis	6	0.55	2014
Pattern generation for Mutation Analysis using Genetic Algorithms	2	0.36	2013
Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays	1	0.36	2013
On reconfigurable Single-Electron Transistor arrays synthesis using reordering techniques	13	0.78	2013
Sensitization criterion for threshold logic circuits and its application	2	0.41	2013
Error Injection & Correction : An Efficient Formal Logic Restructuring Algorithm	0	0.34	2012
A probabilistic analysis method for functional qualification under mutation analysis	4	0.43	2012
Using "Learning Video Portfolio" to Enhance Students' Metacognition in Authentic Learning	0	0.34	2012
On rewiring and simplification for canonicity in threshold logic circuits	7	0.57	2011