Name
Abstract | ||
|---|---|---|
In this paper, we propose a novel on-chip circuit to measurethe jitter present at the output of Phase-Locked-Loops(PLLs) used for synthesizing a clock with equal or higherfrequency than the input clock.This measure is performedat every period of the ... |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/IOLTS.2004.29 | IOLTS |
Keywords | Field | DocType |
digital systems,time domain faults,novel on-chip circuit,input clock,jitter present,critical path,time domain,voltage,transient response,logic circuits,modeling and simulation,random testing | Time domain,Transient response,Modeling and simulation,Computer science,Voltage drop,Modulation,Real-time computing,Electronic engineering,Verilog,Fault injection,Logic element | Conference |
ISBN | Citations | PageRank |
0-7695-2180-0 | 4 | 0.44 |
References | Authors | |
13 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| D. Barros Junior | 1 | 4 | 0.44 |
| F. Vargas | 2 | 17 | 2.17 |
| M. B. Santos | 3 | 67 | 6.87 |
| I. C. Teixeira | 4 | 163 | 20.29 |
| J. P. Teixeira | 5 | 17 | 1.13 |