Paper Info
Title
Optimized Data-Reuse in Processor Arrays
Abstract
In this paper, we present a method for co-partitioning affine indexed algorithms resulting in a Processor Array with an optimized data-reuse. Through this method, a memory hierarchy with an optimized data transfer is derived which allows a significant reduction of the power consumption caused by memory accesses. Apart from former design flows which begin with a space-time transformation, we start with the co-partitioning of the iteration space. This allows an adaption of the resulting Processor Array towards the constraints of the target architecture at the beginning of the design. We illustrate our method for the full search motion estimation algorithm which bears a high potential of data-reuse.
Year
DOI
Venue
2004
10.1109/ASAP.2004.30
ASAP
Keywords
Field
DocType
high potential,optimized data-reuse,processor arrays,optimized data transfer,former design flow,full search motion estimation,memory access,memory hierarchy,processor array,iteration space,co-partitioning affine,motion estimation,design flow,parallel algorithms,indexation,data transfer,space time
Affine transformation,Memory hierarchy,Data transmission,Parallel algorithm,Computer science,Processor array,Parallel computing,Real-time computing,Design flow,Power consumption,Data reuse
Conference
ISSN
ISBN
Citations 
1063-6862
0-7695-2226-2
6
PageRank 
References 
Authors
0.57
5
2
Name
Order
Citations
PageRank
Sebastian Siegel1294.16
Renate Merker215920.59