Name
Abstract | ||
|---|---|---|
III–V and germanium (Ge) field-effect transistors (FETs) have been studied as candidates for post Si CMOS. In this paper, the performance of various digital blocks and static random access memory (SRAM) with different combinations of Si, III–V and Ge devices are studied. SPICE-compatible III–V n-channel FET (nFET) and Ge p-channel FET (pFET) models are developed for the analysis. The delay and energy of the different combinations are estimated and compared. In typical digital design, the driving capability of the nFET and pFET should be matched for optimum noise margin and performance. The combination of III–V nFET with low input capacitance and Ge pFET achieves the best energy-delay performance for many digital logic circuits. The read margin of SRAM is maximized with a Si pass-gate, and an inverter of III–V nFET and Ge pFET. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2210450 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
germanium,field-programmable gate array (fpga),logic circuits,iii-v semiconductors,p-channel fet,germanium field-effect transistor,iii–v,iii-v nfet,si,random-access storage,iii-v device,post silicon cmos,ge,static random access memory,germanium (ge),digital block,adder,silicon,digital logic circuit,field effect transistors,sram,spice,iii-v n-channel fet,pfet,invertors,circuit performance,cmos memory circuits,inverter,optimum noise margin,logic gates,noise,capacitance | Inverter,Logic gate,Capacitance,Field-effect transistor,Computer science,Electronic engineering,Static random-access memory,CMOS,Noise margin,Transistor,Electrical engineering | Journal |
Volume | Issue | ISSN |
21 | 7 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeongha Park | 1 | 0 | 0.68 |
| Saeroonter Oh | 2 | 0 | 0.68 |
| Soyoung Kim | 3 | 168 | 22.15 |
| H.-S. Philip Wong | 4 | 645 | 106.40 |
| S. Simon Wong | 5 | 332 | 40.81 |